Digital Library


Search: "[ author: Jeong Gang Min ]" (2)
    Computer Graphics & The Design of 10-bit 200MS/s CMOS Parallel Pipeline A/D Converter
    Jeong Gang Min The KIPS Transactions:PartA, Vol. 11, No. 2, pp. 195-202, Apr. 2004
    10.3745/KIPSTA.2004.11.2.195

    Computer Graphics & Design of Low Voltage 1.8V, Wide Range 50~500MHz Delay Locked Loop for DDR SDRAM
    Gu In Jae , Jeong Gang Min The KIPS Transactions:PartA, Vol. 10, No. 3, pp. 247-254, Aug. 2003
    10.3745/KIPSTA.2003.10.3.247